Field
This invention relates generally to a method for fabricating a field effect transistor (FET) including a double-recess gate structure and, more particularly, to a method for fabricating an FET including a double-recess gate structure, where the method includes self-aligning the double-recess gate using a single photoresist layer.
Discussion
Field-effect transistors (FET) are well known in the transistor art, and come in a variety of types, such a HEMT, MOSFET, MISFET, FinFET, etc., and can be integrated as horizontal devices or vertical devices. A typical FET will include various semiconductor layers, such as silicon, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium nitride (GaN), indium phosphide (InP), etc. Sometimes the semiconductor layers are doped with various impurities, such as boron and silicon, to increase the population of carriers in the layer, where the higher the doping level of the layer the greater the conductivity of the particular semiconductor material. An FET will also include a source terminal, a drain terminal and a gate terminal, where one or more of the semiconductor layers is a channel layer and is in electrical contact with the source and drain terminals. An electrical potential provided to the source terminal allows electrical carriers, either N-type or P-type, to flow through the channel layer to the drain terminal. An electric signal applied to the gate terminal creates an electrical field that modulates the carriers in the channel layer, where a small change in the gate voltage can cause a large variation in the population of carriers in the channel layer to change the current flow from the source terminal to the drain terminal.
Integrated circuits are typically fabricated by epitaxial fabrication processes that deposit or grow the various semiconductor layers on a semiconductor substrate to provide the circuit components of the device. Substrates for integrated circuits include various semiconductor materials, such as silicon, InP, GaAs, etc. As integrated circuit fabrication techniques advance and become more complex, more circuit components are able to be fabricated on the substrate within the same area and be more closely spaced together. Further, these integrated circuit fabrication techniques allow the operating frequencies of the circuit to increase to very high frequencies, well into the GHz range.
In a typical FET device, the source terminal and the drain terminal are usually fabricated on a heavily doped cap layer to provide a better conductive path to the channel layer. For certain FET devices, higher performance can be achieved by forming a recess through the heavily doped layer and fabricating the gate terminal in the recess so that it is closer to the channel layer. By placing the gate terminal closer to the channel layer, the transconductance Gm of the device is improved by providing more effective control of the charge in the channel layer, which provides faster switching times. It is further known in the art to provide a double-recess gate structure in an FET device, where a wide upper recess is formed through the cap layer of the device and a narrow lower recess is provided through the upper recess. The double-recess gate structure improves the breakdown voltage of the device because the electric field is more distributed across the channel layer so as to prevent a higher voltage drop directly below the gate terminal, which would otherwise cause a high-breakdown voltage and possibly higher device failure. By providing a higher breakdown voltage, the operation of the device is more flexible and can be used for higher power applications.
Most processes known in the art for fabricating FET devices having a double-recess gate structure include employing two photolithography patterning steps to separately form the upper recess and the lower recess, where both of the photolithography patterning processes requires depositing a photoresist mask, etching through the mask, and then removing the remaining portions of the mask.
In order for proper device performance, the recesses need to be aligned relative to each other as best as possible so that the upper recess is directly at the center of the lower recess. If the upper recess is misaligned relative to the lower recess, it is more likely that the gate terminal will contact the heavily doped cap layer, possibly causing an electrical short. For devices that operate at relatively low frequencies, the upper recess can be made relatively large, which allows some error in the alignment of the lower recess. As the devices get smaller and operate at higher frequencies, the size of the recesses also get smaller, which requires tighter alignment procedures.